Counters & Frequency Division

A clock is, at heart, a machine for dividing one fast, steady tick down into slow, meaningful ones. The mains gives the KABtronics clock a relentless 60 pulses every second; the display needs the seconds digit to advance once a second, the tens-of-seconds digit once every ten seconds, the minutes once every sixty, and so on up to hours. Every one of those divisions is done the same way — by chaining toggle flip-flops and steering their clocks with a little diode logic — and this volume is about exactly that machinery: the counters, and the frequency-divide chain they form.

The building block underneath all of it is the toggle flip-flop of Vol 3 (the cross-coupled transistor pair with its 220 pF / 100 kΩ edge-trigger network) and the three diode gates of Vol 3 — AND, OR, and the combined And-Or “selector.” This volume takes those as given and shows what happens when you put them in a row: first the natural divide-by-2, -4, -8, -16 of a plain chain; then the steering logic that bends a /16 chain into the /10, /6, and /12 counters the clock actually uses; and finally the whole divide chain from the 60 Hz line down to the hours digit, including the fast-set tap that lets you run a digit forward by hand. Each counter’s binary output is then handed off to the decoders of Vol 5, which turn it into a lit numeral.

4.1 From a toggle flip-flop to a divider

A toggle flip-flop does one thing: every time its clock input falls — goes from high to low, the falling edge — it changes state. If it was holding a 0 it becomes a 1; if it was holding a 1 it becomes a 0. Nothing happens on the rising edge, and nothing happens while the clock sits still; the flip-flop only flips on that one downward transition.¹

Watch its output, call it Q, while you feed it a steady clock:

• Clock falls (pulse 1): Q goes 0 → 1.
• Clock falls (pulse 2): Q goes 1 → 0.
• Clock falls (pulse 3): Q goes 0 → 1.
• Clock falls (pulse 4): Q goes 1 → 0.

Q completes one full cycle (0, 1, 0) for every two input pulses. The output is a square wave at exactly half the input frequency — a single toggle flip-flop is a divide-by-2. That is the whole trick, and everything else is repetition of it.

4.1.1 Chaining: divide by 2^N

Now feed the Q output of the first flip-flop into the clock of a second. The second one only sees a falling edge when the first one’s Q falls — which happens once every two input pulses — so the second flip-flop toggles at one-quarter the input rate. Its output divides by 4. Add a third clocked from the second and you divide by 8; a fourth divides by 16. In general:

A chain of N toggle flip-flops, each clocking the next, divides the input frequency by 2^N: one flip-flop ÷2, two ÷4, three ÷8, four ÷16.

This is also a binary counter, and that is the key to reading it. If you call the four outputs Q0, Q1, Q2, Q3 and give them the binary place-values 1, 2, 4, 8, then at any moment the four bits together spell out, in binary, how many input pulses have arrived since the last reset. Q0 is the least-significant bit (it toggles every pulse), Q3 the most-significant (it toggles only every eighth). After pulse 6, for instance, the chain reads Q3 Q2 Q1 Q0 = 0110 = 4 + 2 = 6.

4.1.2 Why a raw chain counts to sixteen — and why that is wrong for a clock

Four bits have sixteen combinations, 0000 through 1111, so a free-running four-flip-flop chain counts 0, 1, 2, … , 15 and only then rolls over to 0 — it is a natural ÷16. That is fine if you want sixteen; it is useless for a decimal clock, where every digit must count 0 through 9 and roll over on the tenth pulse (and the tens-of-seconds and tens-of-minutes digits must count only 0 through 5). The job of the rest of this volume is to make a chain that wants to count to sixteen instead count to ten, or six, or twelve. You do not change the flip-flops; you change which clock each flip-flop sees, using gates that watch the count and cut the chain short at the right moment.

4.2 The decade counter (÷10) in full

The decade counter — divide-by-ten — is the workhorse of the clock: it is the seconds digit and the minutes digit, and the same idea (with different masking) makes every other counter. It is four toggle flip-flops, Q0–Q3, exactly as in §4.1, plus four pieces of clock steering. Read the count table first; it is the map for everything that follows.

4.2.1 The count table

These are the only ten states a decade counter is ever allowed to occupy. Read each row as a binary number with Q3 = 8, Q2 = 4, Q1 = 2, Q0 = 1; the rightmost column confirms the sum.

Table 1 — 4.2.1 The count table

Count	Q3 (8)	Q2 (4)	Q1 (2)	Q0 (1)	= sum
0	0	0	0	0	0
1	0	0	0	1	1
2	0	0	1	0	2
3	0	0	1	1	3
4	0	1	0	0	4
5	0	1	0	1	5
6	0	1	1	0	6
7	0	1	1	1	7
8	1	0	0	0	8
9	1	0	0	1	9
→ 0	0	0	0	0	0

Two features of this table drive the whole steering design. First, for counts 0 through 7 the table is identical to a plain binary ÷16 chain — Q0 toggles every pulse, Q1 every two, Q2 every four. Nothing special is needed up to 7. Second, the table breaks from binary at 8: a plain chain would go 7 = 0111 → 8 = 1000 and then keep climbing 9 = 1001, 10 = 1010, 11 = 1011, … . The decade counter must instead go 9 = 1001 → 0 = 0000, skipping the six states 1010 through 1111. The steering logic exists precisely to (a) hold Q1 and Q2 down during counts 8 and 9, and (b) clear Q3 back to 0 on the tenth pulse. The KABtronics design does this by steering the clocks, not by force-resetting the flip-flops.²

4.2.2 The steering logic, flip-flop by flip-flop

Four flip-flops, four clock sources:

• Q0’s clock = the input clock, directly. Q0 is the least-significant bit and must toggle on every input pulse — 0,1,0,1,… all the way up. No gating; the incoming clock drives it straight.
• Q2’s clock = Q1, directly. In the 0–7 region the count is pure binary, so Q2 (the “4” bit) should toggle whenever Q1 (the “2” bit) falls — exactly the plain-chain relationship. Tapping Q2’s clock straight off Q1 gets that for free, and because Q1 is held still during 8 and 9 (next bullet), Q2 correctly stays at 0 there too.
• Q1’s clock = like Q0’s, but masked at count 9. Q1 normally toggles every time Q0 falls — that is the plain ÷4 behavior and it is right for counts 0 through 7. The problem is the pulse that ends count 9: there Q0 falls (9 = …01 → 0 = …00), and a plain chain would let that edge toggle Q1 up to make the binary “10” (1010). We must mask that one edge. The fix is an AND gate feeding Q1’s clock with two inputs: Q0 and NOT-Q3. For counts 0–7, Q3 is 0 so NOT-Q3 is 1, the AND passes Q0 through, and Q1 toggles normally. At counts 8 and 9, Q3 is 1 so NOT-Q3 is 0, the AND output is stuck low, and the falling edge of Q0 at the end of 9 never reaches Q1 — so Q1 stays at 0 and the illegal 1010 state is never entered.
• Q3’s clock = an And-Or “selector,” steered by Q3 itself. Q3 (the “8” bit) has to do two different things depending on where the count is. For counts 0–7 it must behave like the top of a plain chain — go high on the pulse that takes 7 → 8 — which means clocking like Q2 would (off the carry out of the lower bits). For counts 8–9 it must instead come down on the tenth pulse, i.e. behave like Q0 and toggle on the input edge. A single And-Or gate (the “selector” of Vol 3) picks between these two clock sources, and the thing steering the selector is Q3 itself: while Q3 is low the selector routes the “count-up to 8” edge; once Q3 is high (during 8 and 9) the selector routes the input edge that will clear it back to 0 on the tenth pulse.

The net effect is the table in §4.2.1: a counter that climbs 0–7 as plain binary, sets Q3 on the eighth pulse, holds Q1 and Q2 down through 8 and 9, and clears Q3 on the tenth pulse to land back at 0000.

4.2.3 Walking the count, 0 → 9 → 0

It is worth tracing once, pulse by pulse, to see where each flip-flop toggles (a falling edge into a flip-flop is what makes it change). Start reset, at 0000:

1. Pulse 1 (0→1): Q0 toggles 0→1. State 0001.
2. Pulse 2 (1→2): Q0 falls 1→0; that edge clocks Q1, which toggles 0→1. State 0010.
3. Pulse 3 (2→3): Q0 toggles 0→1. State 0011.
4. Pulse 4 (3→4): Q0 falls; clocks Q1 (1→0); Q1’s fall clocks Q2 (0→1). State 0100.
5. Pulse 5 (4→5): Q0 toggles 0→1. State 0101.
6. Pulse 6 (5→6): Q0 falls; Q1 toggles 0→1. State 0110.
7. Pulse 7 (6→7): Q0 toggles 0→1. State 0111.
8. Pulse 8 (7→8): Q0 falls; Q1 falls; Q2 falls; that cascade carries up through the selector to set Q3 (0→1) while Q2 and Q1 clear. State 1000 — Q3 is now high.
9. Pulse 9 (8→9): Q3 is high, so NOT-Q3 = 0 and Q1’s AND gate is blocked. Q0 simply toggles 0→1. Q1, Q2 stay down. State 1001.
10. Pulse 10 (9→0): Q0 falls 1→0. Q1’s gate is still blocked, so Q1 does not toggle. But with Q3 high the selector has routed the input edge to Q3’s clock, so this falling edge clears Q3 (1→0). State 0000 — and the very fall of Q3 here is the carry pulse into the next stage.

So Q3 is high only during counts 8 and 9 (two counts), and it pulses once for every ten input pulses. That falling edge of Q3 on the tenth pulse is exactly the slow tick the next counter needs.

4.2.4 Q3 as the carry into the next stage

Because Q3 falls exactly once per ten input pulses, Q3 is the clock for the next counter. Wire the seconds counter’s Q3 into the clock of the tens-of-seconds counter and the tens digit advances once for every ten seconds — the cascade is automatic. This is the single most important idea in the chain: each counter’s top bit is the next counter’s clock, so dividing by ten then by six then by ten… is just counters clocked in series. Each counter’s four bits Q0–Q3, meanwhile, fan out sideways into the decoders of Vol 5, which read the binary number and light the matching numeral.

4.3 The ÷6 and ÷12 counters — same technique, different masking

The tens-of-seconds and tens-of-minutes digits only ever show 0 through 5; the hours digit shows 1 through 12. Both are built the same way as the decade counter — toggle flip-flops with their clocks steered by AND / And-Or gates — and differ only in where the count is cut short (the masking) and, for hours, in what value it resets to.

4.3.1 Divide-by-six (0–5)

A divide-by-six counter needs only the states 0 through 5 — 000, 001, 010, 011, 100, 101 — so it can be built from three toggle flip-flops (three bits reach 0–7) with steering that forces the rollover to happen on the sixth pulse instead of the eighth. Conceptually it is the decade idea with the cut moved earlier: the count climbs as plain binary 0–5, and on the pulse that would make 6 the steering clears the counter back to 000 instead, so 5 → 0 is the rollover and the top bit pulses once per six inputs. That once-per-six pulse is the carry into the next digit, just as Q3 was for the decade counter.

The KABtronics manual presents the ÷6 counter as the same steering technique with different masking rather than spelling out every gate, and this deep dive does not invent the exact gate wiring it does not give. The principle is certain — toggle flip-flops with clock steering, rolling over on the sixth count; the precise AND / And-Or arrangement that masks counts 6 and 7 is not detailed in the source and should be read off the schematic (Vol 9) for a literal build.

4.3.2 Divide-by-twelve (the hours, 1–12)

The hours stage is the irregular one: it must run 1, 2, … , 12 and then roll back to 1 (not 0), and on a 12-hour clock the tens-of-hours digit is only ever blank-or-1. It is again built from toggle flip-flops with steered clocks — the same technique — but the masking has to do two extra jobs the decimal counters do not: roll over after twelve counts rather than ten or six, and reset to 1 rather than 0 so the display never shows “0 o’clock.” As with the ÷6 counter, the manual describes this at the level of “the same divide-and-steer idea, with the masking set for twelve,” and the exact gate-level steering for the ÷12 / hours stage is not given in the source — treat the gate detail as a read-it-off-the-schematic item (Vol 9), and treat as certain only the behavior: a 1-through-12 count that clocks once per twelve inputs and resets to 1.

A note on transistor counts. The manual does not break out an exact transistor count per counter stage, and this volume does not estimate one — each stage is “three-or-four toggle flip-flops plus a handful of diode gates,” and the cross-coupled-pair transistor cost of a flip-flop is the subject of Vol 3, not a per-stage tally here.

4.4 The full clock divide chain

Now assemble the whole spine. The clock takes the 60 Hz mains (extracted and filtered into a clean square wave by the timebase of Vol 6) and divides it, stage by stage, down to a once-per-second tick and then on into the time digits. Each arrow below is “the previous stage’s carry bit clocks the next stage,” exactly the Q3-into-next-clock idea of §4.2.4.

4.4.1 The prescaler: 60 Hz → 1 Hz

The seconds digit must advance once per second, but the line gives 60 pulses per second, so the first job is to divide 60 Hz down to 1 Hz. That is done in two steps:

• ÷10 takes 60 Hz down to 6 Hz — a decade counter exactly like §4.2, used purely as a divider (its digits are not displayed).
• ÷6 takes 6 Hz down to 1 Hz — the ÷6 counter of §4.3.1, again used purely as a divider.

Together those two stages are the prescaler: 60 → 6 → 1. The output is a clean one-pulse-per-second tick, and that is what clocks the visible time counters. (60 = 10 × 6, which is why the prescaler is a ÷10 followed by a ÷6 — the same two counter types the display uses, just wired as a frequency divider ahead of it.)

4.4.2 Seconds → tens → minutes → tens → hours

From the 1 Hz tick the displayed time falls out as a cascade of the counters above:

1. Seconds — ÷10 (0–9). Clocked at 1 Hz; advances once a second. Carry (its Q3) fires once every ten seconds.
2. Tens of seconds — ÷6 (0–5). Clocked by the seconds carry; advances once every ten seconds, rolls 0–5. Carry fires once every sixty seconds.
3. Minutes — ÷10 (0–9). Clocked by the tens-of-seconds carry; advances once a minute. Carry fires once every ten minutes.
4. Tens of minutes — ÷6 (0–5). Clocked by the minutes carry; advances once every ten minutes. Carry fires once every sixty minutes — once an hour.
5. Hours — ÷12 (1–12). Clocked by the tens-of-minutes carry; advances once an hour, runs 1 through 12, resets to 1.

Read top to bottom that is HH : MM : SS, and the whole display is nothing but six counters clocked one from the next, each feeding its decoder. The chain matches the one-line spine of Vol 1: 60 Hz → ÷10 → ÷6 → 1 Hz → seconds → tens → minutes → tens → hours.

4.4.3 The 2 Hz fast-set tap and the H / M switches

Setting the clock by waiting for the minutes to crawl around at one-per-minute would be intolerable, so the design provides a fast-set path. A 2 Hz tap is taken from inside the prescaler — a point in the divide chain running at two pulses per second — and routed to the set switches as a fast tick.³

The two front-panel Set switches (H and M) work by substituting that fast tick for the normal carry into a counter. Normally the minutes counter is clocked by the tens-of-seconds carry (once a minute) and the hours counter by the tens-of-minutes carry (once an hour). Press M and the minutes counter is fed the 2 Hz tap instead of its normal carry, so the minutes run forward at two-per-second until you let go — fast enough to set in a few seconds, slow enough to stop on the right value. Press H and the hours counter is likewise fed the fast tick and the hours spin up. In gate terms this is one more use of the And-Or selector: the switch steers the counter’s clock between “normal carry from the stage below” and “fast 2 Hz set tick,” which is the same selector pattern that bends the counters themselves.

4.5 How the counters hand off to the decoders

Each counter presents the rest of the clock with a four-bit binary number on Q3 Q2 Q1 Q0 (three bits for the ÷6 stages). That number is the digit to display, in binary — and turning “0110” into a lit “6” on a seven-segment LED is the job of Vol 5: a one-of-N diode decoder selects which numeral is active, and a seven-segment diode decoder lights the right segments for it. The counter does not know or care about segments; it just counts and exposes its bits. This clean split — count in binary here, decode to a glyph there — is what lets the same decade counter serve as a prescaler divider in one place and a displayed seconds digit in another. The flip-flops and gates that make each counter are Vol 3; the decoders the counters feed are Vol 5; this volume is only the counting and dividing in between.

4.6 References (Vol 4)

• KABtronics Transistor Wall Clock Kit — assembly manual (“Theory of Operation,” circuit description) and 15-page schematic, in 02-inputs/LED_Transistor_Clock/. Vendor: http://www.transistorclock.com.
• Cross-references: the toggle flip-flop and diode gates (Vol 3); the one-of-N and seven-segment decoders the counters feed (Vol 5); the 60 Hz mains timebase that drives the chain (Vol 6); the one-line signal chain and volume index (Vol 1).

Footnotes

1. The falling-edge toggle behavior, the cross-coupled bistable, and the 220 pF / 100 kΩ edge-trigger network are developed in Vol 3 (Transistor-Level Building Blocks). This volume takes the toggle flip-flop and the diode AND / OR / And-Or (“selector”) gates as given building blocks. Source: Transistor Clock Assembly Manual, KABtronics (transistorclock.com), “Theory of Operation.” ↩

2. The decade-counter steering — Q0 clocked directly by the input, Q2 by Q1, Q1 by an AND of Q0 and NOT-Q3 to mask the count-9 edge, and Q3 by an And-Or selector steered by Q3 — follows the manual’s “Theory of Operation” description of how the natural ÷16 flip-flop chain is bent into a ÷10. The count table (Q3 Q2 Q1 Q0 vs 0–9) is the standard 8-4-2-1 binary weighting. ↩

3. The 2 Hz fast-set tap and the H / M Set switches that substitute the fast tick for a counter’s normal carry are described functionally in the manual. The exact gate wiring of the ÷6 and ÷12 counters, and the precise point the 2 Hz tap is taken from, are read off the 15-page schematic (Vol 9) rather than spelled out gate-by-gate in the theory text; where the manual does not detail the gates this volume says so rather than inventing them. ↩