Transistor-Level Building Blocks

Every flip-flop, gate, counter, and decoder in this clock is built from the same five circuits, and those five are in turn built from one device used in one way: the bipolar transistor as an on/off switch. This is the volume the rest of the series leans on. Once you can read a transistor as a switch, a pair of diodes as an AND gate, and a cross-coupled pair as a one-bit memory, the counters (Vol 4), the decoders (Vol 5), and the timebase (Vol 6) are just those blocks repeated and wired together. Nothing here needs an oscilloscope or a SPICE deck to follow — it is the KABtronics manual’s own “Circuit Description,” worked through with the arithmetic shown.¹

We move in the order the clock itself is assembled in your head: first the three electrical tools (Ohm’s law, the RC charge curve, the diode), then the transistor switch, then logic gates made from diodes, then the bistable that holds a bit, then the edge-trigger that turns the bistable into a counter stage, and finally the comparator that cleans up the mains. Every number below is from the manual or from standard theory, and every approximate value is labelled as such.

3.1 Three electrical tools

Before any transistor, three pieces of first-year electronics. They are the only physics the whole clock needs.

3.1.1 Ohm’s law

The single most-used equation on the board: the voltage across a resistor equals the current through it times its resistance,

V = I × R.

Rearranged, I = V / R and R = V / I. Currents on this board are small. A 10 kΩ resistor with the full 12 V rail across it passes

I = V / R = 12 V / 10 000 Ω = 1.2 mA,

and that 1.2 mA figure recurs all over the clock, because 10 kΩ to the +12 V rail is the default collector- and base-resistor value. Drop the rail across a 1 kΩ and you get 12 mA; across a 1 MΩ, 12 µA. Keep that scaling in mind and most of the currents below you can estimate in your head.

3.1.2 The RC charge curve

Put a resistor in series with a capacitor and apply a step of voltage, and the capacitor charges through the resistor. At the instant the step is applied the cap is empty and acts like a short, so the full step voltage appears across the resistor and a current of V / R flows. As charge piles onto the cap, the voltage across it rises toward the rail and the voltage across the resistor decays toward zero — the current tapers off. The speed of all this is set by the product R × C (the “time constant,” in seconds when R is in ohms and C in farads): bigger R or bigger C, slower charge. This is the entire basis of the edge-trigger network in §3.6 — a small cap and a large resistor that, at the moment an edge arrives, briefly passes a spike and then settles back to zero.

3.1.3 The diode

A diode is a one-way valve for current. Forward-biased (anode positive with respect to cathode) it conducts and drops a roughly fixed ≈ 0.7 V across itself regardless of the current — that 0.7 V is the number to remember. Reverse-biased it blocks: essentially no current flows, so if a diode sits in series with a resistor and is reverse-biased, the full rail appears across the diode and 0 V across the resistor (no current, no I × R drop). Both behaviors are load-bearing: the 0.7 V forward drop is what makes the diode gates of §3.4 pull a node up or down, and the reverse-blocking is what lets a low input “win” a gate by isolating the high inputs.

3.2 The transistor as a switch — “a pair of diodes with a trick”

The kit uses two complementary bipolar transistors: the 2N3904 (NPN) and the 2N3906 (PNP), each with a current gain β ≈ 50. A bipolar transistor behaves, to first order, like a pair of diodes back-to-back sharing the base — but with a trick: the current you push into the base-emitter diode is multiplied. A base current I_B lets a collector current of up to β × I_B flow. That multiplication is the whole game.

Used as a switch, an NPN works like this. The emitter sits at ground. If the base input is below ≈ 0.7 V, the base-emitter diode does not conduct, no base current flows, no collector current flows, and the collector — pulled up to +12 V through its collector resistor — floats high. If the input rises above ≈ 0.7 V, base current flows, the transistor turns on, and the collector is pulled down through its collector resistor toward ground. High input → low output; low input → high output. That inversion is the seed of every gate and latch.

3.2.1 The manual’s worked example

The manual works one specific case, and it is worth doing the arithmetic with units. Apply 1.7 V to the base through a 10 kΩ base resistor. The base sits a diode-drop above the grounded emitter — about 0.7 V — so the voltage across the base resistor is the input minus that drop:

V_R(base) = 1.7 V − 0.7 V = 1.0 V, I_B = V_R / R = 1.0 V / 10 000 Ω = 0.1 mA.

With β ≈ 50, the collector can sink up to

I_C(max) = β × I_B = 50 × 0.1 mA = 5 mA.

That is the capacity of the switch given this base drive. How much it actually conducts is set by the collector load. With a 10 kΩ collector resistor to +12 V, pulling the collector all the way to ground would draw

I_C = 12 V / 10 000 Ω = 1.2 mA,

and 1.2 mA is well under the 5 mA the transistor can sink, so the transistor easily wins: the collector is dragged down close to ground (the transistor is “saturated”). The switch is firmly on, with margin to spare — that 5 mA-vs-1.2 mA headroom is exactly the design comfort that lets these stages drive one another reliably.

3.2.2 The PNP as the high-side complement

The 2N3906 PNP is the mirror image and is used as a high-side switch — it connects a load to the positive rail rather than to ground. Its emitter sits at (or near) +12 V, and it turns on when its base is pulled about 0.7 V below the emitter, i.e. when the base is driven low. So where an NPN turns on with a high input and sources nothing but sinks to ground, a PNP turns on with a low input and sources current down from the rail. The two together — NPN pulling down, PNP pulling up — are the complementary pair that lets the clock both light a load and steer a node in either direction. β ≈ 50 and the same Ohm’s-law arithmetic apply; only the polarities flip.

3.3 From one switch to logic

A single switch already inverts. To compute — to combine two signals into one — the clock uses diode logic for the AND and OR functions and reserves transistors for inversion, memory, and gain. This split is the classic “diode-transistor” style: diodes are cheap, take no power when idle, and a resistor finishes the gate. The next section builds the three gates the counters and decoders actually use. Throughout, treat a logic 1 (“high”) as near the +12 V rail and a logic 0 (“low”) as near ground, and remember the two diode facts from §3.1.3: a forward diode drops ≈ 0.7 V, a reverse diode blocks and isolates.

3.4 Gates from diodes and a resistor

3.4.1 The AND gate

Take two diodes with their cathodes tied to the two inputs A and B, join their anodes to a common node, and pull that node up to +12 V through a 10 kΩ resistor. The node is the output.

• If either input is low (near ground), that input’s diode is forward-biased and conducts, clamping the node down to roughly one diode-drop above the low input — the node is low. The low input “wins” by pulling current through the pull-up resistor.
• Only when both inputs are high does neither diode conduct (both are reverse-biased or off), the pull-up sees no load, and the node floats high.

Output high only when A and B are high — an AND gate. The pull-up current when an input is low is the familiar 12 V / 10 kΩ ≈ 1.2 mA through the resistor.

Table 1 — 3.4.1 The AND gate

A	B	Out (A AND B)
0	0	0
0	1	0
1	0	0
1	1	1

3.4.2 The OR gate

Flip the diodes and the resistor. Tie the two diodes’ anodes to the inputs, join their cathodes to the output node, and pull that node down to ground through a resistor.

• If either input is high, that input’s diode conducts and pulls the node up to about a diode-drop below the high input — the node is high.
• Only when both inputs are low is there nothing to lift the node, and the pull-down holds it low.

Output high when A or B is high — an OR gate.

Table 2 — 3.4.2 The OR gate

A	B	Out (A OR B)
0	0	0
0	1	1
1	0	1
1	1	1

3.4.3 The AND-OR gate

The counters need a slightly bigger primitive: (A AND B) OR (C AND D). Build it by combining the two above — two AND gates whose outputs feed one OR gate. Concretely, two diode AND pairs each produce a node that is high only when its own two inputs are both high; those two nodes are then OR’d by a second diode stage into the final output. The output is high when A and B are both high, or C and D are both high (or both pairs are). This single gate is the “selector” at the heart of each decade counter — it is what lets a chain of flip-flops divide by ten instead of by sixteen by steering the count at the right moment (Vol 4). The same diode-AND idea is reused, at much larger fan-in, in the one-of-ten and seven-segment decoders (Vol 5).

Table 3 — 3.4.3 The AND-OR gate

A	B	C	D	(A AND B)	(C AND D)	Out
0	0	0	0	0	0	0
1	1	0	0	1	0	1
0	0	1	1	0	1	1
1	0	1	1	0	1	1
1	1	1	1	1	1	1
1	0	0	1	0	0	0

FIGURE SLOT 3.6 — A close-up macro photo of a populated corner of the KABtronics board showing rows of small-signal diodes and 10 kΩ resistors forming a diode-logic matrix, to make the “gates are just diodes and resistors” point concrete. Source hint: owner’s own build photo once the board is populated, or a license-clean Wikimedia/Openverse macro of diode-array PCB construction (credit verbatim per the photo policy).

3.5 The bistable — how two transistors hold one bit

Memory is where the transistor earns its keep. Take two NPN switches, each with a 10 kΩ collector resistor to +12 V, and cross-couple them: the collector of Q1 feeds the base of Q2 through a 10 kΩ resistor, and the collector of Q2 feeds the base of Q1 through another 10 kΩ. Call the two collectors output A and output B. This circuit has exactly two stable states, and that is the point.

Suppose A is high. A high at A means current flows through the coupling resistor into Q2’s base, so Q2 is on and pulls its collector — output B — low. A low at B means no base current reaches Q1, so Q1 is off, and with Q1 off nothing pulls output A down, so the 10 kΩ pull-up holds A high. The state is self-consistent: A high keeps B low keeps A high. It will sit there indefinitely.

The mirror state — B high, A low — is equally self-consistent by the identical argument: B high turns Q1 on, dragging A low, which keeps Q2 off, which lets B stay high. Two stable states, each holding itself: this is a bistable, and it stores exactly one bit. Nothing changes it until something from outside reaches in and tips it over — which is the job of the edge-trigger in the next section.

3.6 The toggle flip-flop — making the bistable count

A bistable that you can only set from outside is a latch. To count, you need it to flip each time a clock pulse arrives — that is a toggle flip-flop, and the trick is a small edge-trigger network bolted onto the bistable’s input.

3.6.1 The edge-trigger network

The network is a 220 pF capacitor in series with the clock input, with a 100 kΩ resistor to the +12 V rail and a 100 kΩ resistor to ground forming a divider at the capacitor’s far side. It is an RC differentiator (§3.1.2): the cap passes only changes in its input, not steady levels. Drive the input with the clock, which swings between 0 V and 12 V, and watch the network’s output:

• On the input’s rising edge (0 → 12 V), the cap couples a brief positive spike — the manual’s waveform shows it overshooting to about +18 V before decaying back toward the resting level as the cap recharges through the 100 kΩ resistors.
• On the input’s falling edge (12 → 0 V), the cap couples a brief negative spike, dipping to about −6 V before recovering.

So a clean square clock in becomes a pair of short spikes out — up on the rise, down on the fall — each lasting only as long as the 220 pF / 100 kΩ network takes to settle.

3.6.2 How the negative spike flips the bit

The flip-flop is wired to act on the falling-edge negative pulse. That brief dip toward −6 V momentarily removes base current from whichever transistor is currently on, releasing its grip on its collector. With the “on” transistor briefly starved, the bistable’s cross-coupling does the rest: the other transistor’s base, no longer held low, gets current and turns on, and when the pulse passes the latch settles into the opposite state. One falling clock edge → one flip. The flip-flop toggles on each falling edge, and because it changes state once per two input edges, its output runs at half the input frequency — it is a divide-by-two.

That single fact scales into the whole clock. Chain four toggle flip-flops so each one clocks the next, and the chain counts 0–15 in binary — divide by sixteen. Add the AND-OR “selector” of §3.4.3 to reset or skip at the right count and the same four flip-flops divide by ten (a decade) or six or twelve — exactly the dividers the time chain needs (Vol 4).

3.7 The comparator — a differential pair that snaps

The last building block is the one that lives at the front door of the clock, where the soft, rounded rectified mains has to be turned into a crisp square wave (Vol 6). That job needs a circuit that decides cleanly between “input above threshold” and “input below,” and the answer is the differential pair with positive feedback.

3.7.1 Current steering in the differential pair

Take two NPN transistors and tie their emitters together through a single tail resistor to ground. Apply a voltage to each base — call them A and B. Whichever base is higher turns its transistor on harder, and because the emitters are shared, that transistor hogs essentially all the tail current while the other is starved off.

The manual’s numbers make it concrete. Put A at 5 V and B at 6 V. The shared emitters sit one diode-drop below the higher base, so the emitter node sits at about

V_E ≈ 6 V − 0.7 V ≈ 5.6 V (held there by B’s transistor, which is on).

Now look at A’s transistor: its base is at 5 V but its emitter is at 5.6 V, so its base-emitter junction is actually reverse-biased by 0.6 V — it is firmly off. B carries the whole tail current, and if the tail resistor passes, say, 0.64 mA at this operating point, then B’s transistor carries ≈ 0.64 mA and A’s carries ≈ 0. The pair has steered all the current to the higher input. Swap the inputs and the current swaps transistors. That is a comparator: the side carrying the current tells you which input is larger.

3.7.2 The positive-feedback snap

A bare differential pair changes hands gradually as the inputs cross, which leaves the output soft and noise-prone right at the threshold — bad for a timebase that must reject mains hash. The fix is a second pair (Q3/Q4) arranged so that as input A rises through B’s level, the circuit slightly lowers point B in response. Lowering B makes A look even more clearly “above” — which lowers B further still. That is positive feedback: a small nudge past the threshold is amplified into a full, fast transition, so the comparator snaps cleanly from one state to the other instead of drifting through the middle. The snap gives a clean edge regardless of how slowly the input crossed, and the same Q3/Q4 stage provides the output. In the clock this is the heart of the 60 Hz timebase extractor, which turns the rectified line into a clean square wave and, in doing so, acts as a brick-wall noise filter (Vol 6).

3.8 The five blocks, assembled

That is the whole vocabulary. Read the rest of the clock as these five circuits repeated:

• The switch (§3.2) inverts and provides gain — every gate, latch, and driver contains it.
• The diode gates (§3.4) compute AND, OR, and AND-OR — the steering logic of the counters (Vol 4) and the matrices of the decoders (Vol 5).
• The bistable (§3.5) holds one bit.
• The toggle flip-flop (§3.6) makes the bistable count; four in a row divide by sixteen, and with a selector, by ten, six, or twelve — the entire divide chain (Vol 4).
• The comparator (§3.7) snaps a soft analog input into a clean edge — the 60 Hz timebase front end (Vol 6).

Everything visible on the KABtronics board is one of these, wired to its neighbors. Vol 4 takes the toggle flip-flop and builds the counters; Vol 5 takes the diode AND and builds the decoders; Vol 6 takes the comparator and builds the timebase. From here on, the clock is assembly, not new physics.

3.9 References

• Ohm’s law, the RC charge curve, the ≈ 0.7 V diode forward drop, and the β-multiplied collector current are standard first-year electronics theory, stated here only as the tools the manual’s circuits use; no values beyond those in the manual are introduced.
• Cross-references: the diode gates and toggle flip-flop feed Vol 4 (Counters & Frequency Division); the diode AND is reused in Vol 5 (Decoders & Seven-Segment Drive); the comparator is the front end of Vol 6 (The Timebase — Mains 60 Hz). Vendor: http://www.transistorclock.com.

Footnotes

1. Transistor Clock Assembly Manual, KABtronics (transistorclock.com), document version 1.4 for PC board version 4, copyright 2011 — “Circuit Description” section. Source of the device types (2N3904 NPN / 2N3906 PNP, β ≈ 50), the ~12–13 V supply rail, the worked switch example (1.7 V into 10 kΩ → 0.1 mA base current → up to 5 mA collector capacity, 1.2 mA to pull a 10 kΩ load to ground), the cross-coupled bistable with 10 kΩ collector and coupling resistors, the 220 pF / 100 kΩ edge-trigger network and its +18 V / −6 V waveform on a 0↔12 V clock, the diode AND / OR / AND-OR gates, and the differential-pair comparator with its 5 V / 6 V example (~5.6 V emitters, ~0.64 mA tail current) and the Q3/Q4 positive-feedback snap. Full manual + 15-page schematic in 02-inputs/LED_Transistor_Clock/. ↩