Cheatsheet & Glossary

This final volume is the laminate-ready synthesis of the whole series: the signal chain in one box, the decade-counter count and steering tables, the transistor building blocks with one-line truths, the display and 7-segment map, the full kit reference (BOM, resistor and capacitor codes, the transistor pinout), a first-light troubleshooting table, and an A–Z glossary. It is meant to sit on the bench while you build, probe, or debug — no prose to wade through, just the tables the earlier volumes earned. Everything here is drawn from the KABtronics Transistor Wall Clock Kit (transistorclock.com) and the textbook circuits it is made from; where a fact is standard reference knowledge rather than a manual quote it is flagged as such, and where the manual is silent that is stated.

This is a 60 Hz design. A 50 Hz mains region needs a different prescaler ratio (§10.2) — everything downstream of the 1 Hz tick is unchanged.

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10.1 The signal chain, in one box

The spine of the entire clock. Read left to right: timebase, prescaler, then the seconds-to-hours counter cascade. At every digit the same four-stage pattern repeats.

60 Hz mains → extract + filter → ÷10 → ÷6 → 1 Hz → [÷10 seconds] → [÷6 tens-sec] → [÷10 minutes] → [÷6 tens-min] → [÷12 hours]

At each digit: counter → one-of-N decode → seven-segment decode → LED

Table 1 — 10.1 The signal chain, in one box

Stage	Divides by	Output	Range shown	Volume
60 Hz extractor + filter	—	clean 60 Hz square	—	Vol 6
Prescaler ÷10	10	6 Hz	—	Vol 4
Prescaler ÷6	6	1 Hz tick	—	Vol 4
Seconds	10	once / 10 s	0–9	Vol 4
Tens of seconds	6	once / 60 s	0–5	Vol 4
Minutes	10	once / 10 min	0–9	Vol 4
Tens of minutes	6	once / 60 min	0–5	Vol 4
Hours	12	once / 12 h	1–12	Vol 4

Net division from 60 Hz to the 1 Hz tick is ÷60 (10 × 6). The six display digits are HH:MM:SS, with single LEDs for the colons (Vol 2).

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10.2 The decade counter — count table and steering logic

A decade counter is four toggle flip-flops (a natural ÷16) plus steering logic that forces it to wrap at ten instead of sixteen (Vol 4). The flip-flops carry binary weights 8-4-2-1 (Q3 Q2 Q1 Q0); each toggles on the falling edge of its clock.

10.2.1 Count table (binary 8-4-2-1)

Table 2 — 10.2.1 Count table (binary 8-4-2-1)

Count	Q3 (8)	Q2 (4)	Q1 (2)	Q0 (1)
0	0	0	0	0
1	0	0	0	1
2	0	0	1	0
3	0	0	1	1
4	0	1	0	0
5	0	1	0	1
6	0	1	1	0
7	0	1	1	1
8	1	0	0	0
9	1	0	0	1
(wrap)	0	0	0	0

Q3 is high at counts 8 and 9 — that is the once-per-ten carry that clocks the next digit up the chain.

10.2.2 Steering logic — what clocks each flip-flop

Table 3 — 10.2.2 Steering logic — what clocks each flip-flop

Flip-flop	Clocked by	Purpose
Q0	the input pulse	counts every edge (÷2)
Q1	AND(Q0, NOT-Q3)	normal ÷2 of Q0, but the NOT-Q3 mask blocks the toggle at count 9 so the counter skips 10–15 and wraps
Q2	Q1	÷2 of Q1
Q3	an AND-OR selector	set high entering 8, used as the carry; the selector resets it cleanly on wrap

A ÷6 counter (tens-of-seconds, tens-of-minutes) is the same idea reset at six; the ÷12 hours counter (1–12, not 0–11) uses an analogous steering set (Vol 4). For a 50 Hz build the prescaler changes from ÷10 then ÷6 to a chain whose product is 50 (e.g. ÷10 then ÷5); the seconds-through-hours counters are identical.

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10.3 Building-blocks quick reference

Everything in the clock is one of these six circuits (Vol 3). The logic family is RTL in spirit — resistor-and-transistor switches plus diode gates.

Table 4 — 10.3 Building-blocks quick reference

Block	Built from	One-line behavior
Transistor switch	1× 2N3904 (NPN) or 2N3906 (PNP), β ≈ 50	base current saturates it → collector pulled to ground; no base current → collector floats up
Diode AND gate	2 diodes + 10 K pull-up	output high only if both inputs high; any low input pulls it down
Diode OR gate	2 diodes + pull-down	output high if either input high
AND-OR gate	AND feeding OR	selects/combines two conditions — used in counter steering
Bistable	2 cross-coupled transistors	holds a 0 or 1 (one bit of memory)
Toggle flip-flop	bistable + 220 pF / 100 K edge trigger	toggles on the falling edge of its clock; ÷2 building block of every counter
Comparator	differential pair + snap feedback	snaps cleanly between states at its threshold — used in the 60 Hz extractor

Gate truth tables (high = 1):

Table 5 — Gate truth tables (high = 1)

A	B	AND	OR
0	0	0	0
0	1	0	1
1	0	0	1
1	1	1	1

Edge trigger: the 220 pF capacitor differentiates the clock edge and the 100 K resistor sets the pulse decay; only the falling edge produces a toggle pulse.

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10.4 The 60 Hz timebase, in one box

The clock has no crystal, no RTC, no battery — it counts mains cycles. Long-term accuracy is excellent (the utility holds the line frequency tightly over days), but there is no holdover: pull the plug and the time is lost; on restore it starts from a reset state and must be set (Vol 6).

bridge leg → comparator vs ~6 V → 60 Hz pulse train → pulser discharges a small cap each edge → cap ramps back up → 2nd comparator vs ~6 V → clean 60 Hz square

Table 6 — 10.4 The 60 Hz timebase, in one box

Property	Value / behavior
Source	one leg of the rectifier bridge
First comparator	trips against ~6 V → raw 60 Hz pulse train
Pulser + cap	each edge discharges a small cap; it ramps back between edges
Second comparator	trips against ~6 V → clean 60 Hz square wave
Filter character	acts as a ~120 Hz brick-wall low-pass: line noise can ramp the cap but cannot manufacture extra edges, so noise cannot add counts
Long-term accuracy	excellent (mains frequency is regulated by the utility)
Holdover on power loss	none — clock loses time when unpowered

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10.5 Display quick-reference

Six statically-driven 7-segment red LED digits (LSD8161-11) plus single LEDs for the colons (Vol 2). Static drive means every lit segment is on continuously — nothing is scanned or multiplexed. Each segment has its own 680 Ω current-limit resistor, and the decoder pulls a segment line low to light it.

Table 7 — 10.5 Display quick-reference

Item	Value / note
Display part	LSD8161-11, red 7-segment (common type not specified in the manual — verify before substituting)
Drive style	static (continuous), not multiplexed
Current limit	one 680 Ω resistor per segment
Decode polarity	active-low — decoder pulls the segment line down
Colons	single discrete LEDs
Orientation hazard	pin 1 is physically missing on the LSD8161-11 — use that gap to orient the part; do not assume a corner
Handling	LED dice are heat-sensitive — solder quickly, avoid prolonged iron contact

10.5.1 Seven-segment map (segment names: a top, b upper-right, c lower-right, d bottom, e lower-left, f upper-left, g middle)

Table 8 — 10.5.1 Seven-segment map (segment names: a top, b upper-right, c lower-right, d bottom, e lower-left, f upper-left, g middle)

Numeral	Segments lit
0	a b c d e f
1	b c
2	a b g e d
3	a b g c d
4	f g b c
5	a f g c d
6	a f g c d e
7	a b c
8	a b c d e f g
9	a b c f g (d)

The (d) on the 9 marks the segment some glyph styles add to close the tail; the map above follows the series’ rendering (Vol 5). The 8 is the all-segments test pattern — a useful first-light check.

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10.6 Kit reference

10.6.1 BOM quick-list

Table 9 — 10.6.1 BOM quick-list

Class	Parts
Transistors	2N3904 (NPN), 2N3906 (PNP) — TO-92, β ≈ 50
Diodes	small-signal (logic) + 4 large rectifier diodes (the bridge)
Resistors	680 Ω, 1 K, 10 K, 100 K, 1 M (5 % carbon film)
Capacitors	220 pF, 0.001 µF, 0.01 µF, 0.1 µF (poly) + one 6,800 µF electrolytic
Displays	LSD8161-11 7-segment red LEDs + single colon LEDs
Switches	H (hours) and M (minutes) set switches

Per-value quantities are not specified in the shared facts — count from the kit’s own parts list. A current kit price is not quoted here — verify at transistorclock.com.

10.6.2 Resistor color-code table (5 %, gold tolerance band)

Table 10 — 10.6.2 Resistor color-code table (5 %, gold tolerance band)

Value	Band 1	Band 2	Multiplier
680 Ω	blue	grey	brown
1 K	brown	black	red
10 K	brown	black	orange
100 K	brown	black	yellow
1 M	brown	black	green

(Standard EIA color-code reference; the 4th band is gold = ±5 %.)

10.6.3 Poly-cap code table

Table 11 — 10.6.3 Poly-cap code table

Printed code	Value
221	220 pF
102	0.001 µF
103	0.01 µF
104	0.1 µF

(Standard 3-digit ceramic/film code: first two digits = significant figures, third = number of zeros, in pF.)

10.6.4 Transistor pinout (TO-92)

Both the 2N3904 and the 2N3906 are TO-92 parts. With the flat face toward you and the leads pointing down, the pins read E–B–C (Emitter, Base, Collector) left to right (Figure 10.1) — the common JEDEC TO-92 ordering for these parts, given here as standard reference, not a manual quotation. The two transistors are visually identical in the same package; read the printed part number to tell NPN (2N3904) from PNP (2N3906).

10.6.5 Polarity reminders (the only two “backwards = damage” parts)

Table 12 — 10.6.5 Polarity reminders (the only two "backwards = damage" parts)

Part	Risk if reversed
6,800 µF electrolytic (≈ 13 V DC across it)	can overheat and vent — observe the − stripe / + lead
4 bridge rectifier diodes	can short and overheat the transformer — observe the cathode band

Everything else on the board is low-voltage and non-polarized or self-orienting; nothing you touch is at line voltage (the mains stays inside the wall transformer).

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10.7 First-light troubleshooting (quick table)

Work one digit at a time, in this order. Each “no” localizes the fault to one of the three stages — counter, one-of-N decode, or 7-segment decode (Vol 9).

Table 13 — 10.7 First-light troubleshooting (quick table)

Ask, in order	If NO → suspect	Stage
1. Is the digit changing at all?	counter not clocking / dead flip-flop / missing carry in	counter
2. Is it changing at the right rate?	wrong divide ratio / steering logic / a stuck flip-flop	counter
3. Does it pass through the right number of states (10, 6, or 12)?	steering / reset logic wrong	counter
4. Are the glyphs correct (right segments per numeral)?	one-of-N or 7-segment decode wiring, or a dead segment/680 Ω	decode / 7-seg

A digit that counts correctly but shows wrong shapes is a decode problem; a digit that shows clean glyphs but in the wrong sequence or rate is a counter problem. The all-on 8 pattern is the fastest segment-integrity check.

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10.8 Source and series map

• Anchor build: KABtronics Transistor Wall Clock Kit — six-digit HH:MM:SS, ~1,256 discrete parts, no ICs, 60 Hz mains timebase, 10 × 11.3 in board, ~5.7 W, 9–12 VAC in (~13 VDC on the 6,800 µF cap).
• Vendor / manual: http://www.transistorclock.com.
• This is a 60 Hz design — a 50 Hz region needs a different prescaler ratio (§10.2); everything downstream of the 1 Hz tick is identical.

Table 14 — 10.8 Source and series map

Vol	Read it for
1	Overview, signal chain, decision tree
2	The LED display and static drive
3	Transistor building blocks (switch, gates, bistable, toggle, comparator)
4	Counters and frequency division (count + steering tables)
5	Decoders and 7-segment drive
6	The 60 Hz mains timebase
7	Building the KABtronics kit
8	Buying a kit or finished clock
9	The collected project and troubleshooting
10	(this volume) cheatsheet and glossary

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10.9 Glossary (A–Z)

Annular ring — the ring of copper around a drilled pad on the PC board; a good ring all the way around is part of a sound solder joint on a through-hole part.

BCD (binary-coded decimal) — a 4-bit code for a single decimal digit 0–9, weights 8-4-2-1; what each decade counter holds and what the decoders read (§10.2).

Beta (β, current gain) — a bipolar transistor’s collector-to-base current ratio; ≈ 50 for the kit’s 2N3904/2N3906. Enough base current to saturate the switch is the whole design target (Vol 3).

Bistable — two cross-coupled transistors that hold one of two stable states; one bit of memory, the core of every flip-flop (§10.3).

Bridge rectifier — four diodes that turn the transformer’s AC into DC for the supply; also the tap point for the 60 Hz extractor (§10.4). Polarity-sensitive (§10.6.5).

Brick-wall filter — a filter with a very sharp cutoff; the extractor’s pulser-and-cap stage behaves as a ~120 Hz brick-wall low-pass so line noise cannot add clock counts (§10.4).

Carry — the once-per-ten (or -six, -twelve) pulse a counter sends to the next digit up the chain; in the decade counter it is Q3 going high at 8–9 (§10.2).

Common anode / common cathode — the two ways a 7-segment LED ties its segments together. The LSD8161-11’s common type is not specified in the manual; the decode is active-low (pulls segment lines down), so verify before substituting (§10.5).

Decade counter — a counter that wraps every ten counts (0–9); four toggle flip-flops plus steering logic (§10.2).

Decoder — diode logic that turns a counter’s 4-bit number into something else: a one-of-N decoder picks the active numeral, a seven-segment decoder lights the right segments for it (Vol 5).

Differential pair — two transistors sharing a common emitter current, comparing two voltages; with snap feedback it forms the extractor’s comparator (§10.3).

Edge trigger — the 220 pF / 100 K network that converts a clock level change into a brief pulse; here it fires on the falling edge to toggle a flip-flop (§10.3).

Flip-flop — a clocked bistable. In this clock, a toggle (T) flip-flop that changes state on each falling clock edge; four in a row are a ÷16 counter (§10.2, §10.3).

Mains-frequency timebase — using the 60 Hz power line itself as the time reference instead of a crystal: excellent long-term accuracy, no holdover when unpowered (§10.4).

Prescaler — the ÷10 then ÷6 stages that bring 60 Hz down to the 1 Hz tick before the seconds counter (§10.1).

RTL (resistor-transistor logic) — a logic family built from resistors and transistor switches (here augmented with diode gates); the discrete style this whole clock is drawn in (§10.3).

Seven-segment — the seven bars (a–g) that form a numeral on an LED digit; the map of which bars light each numeral is in §10.5.1.

Static drive — driving every lit segment continuously (one resistor each), as opposed to multiplexing/scanning; this clock is statically driven (§10.5).

Steering logic — the small AND / AND-OR gates that change a natural ÷16 flip-flop chain into a ÷10, ÷6, or ÷12 counter by masking and resetting toggles (§10.2.2).

Toggle — to change to the opposite state on each clock edge; the action of a T flip-flop and the basis of binary counting (§10.2).

Truth table — a table listing a gate’s output for every input combination; the AND/OR table is in §10.3.

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10.10 References (Vol 10)

• KABtronics Transistor Wall Clock Kit — assembly manual (theory of operation, circuit description, parts identification, troubleshooting, specifications) and the 15-page schematic, in 02-inputs/LED_Transistor_Clock/. Vendor: http://www.transistorclock.com.
• TO-92 pinout (E–B–C), resistor EIA color codes, and 3-digit capacitor codes in §10.6 are given as standard electronics reference, not manual quotations. Items flagged “not specified” / “verify” (kit price, per-value quantities, the LSD8161 common type) are not established by the shared facts and should be confirmed against the kit’s own parts list.