Running It

This volume covers living with the finished clock: what to power it from, how to set it, how well it keeps time, what goes wrong and how to find it. The figures here come from the schematic and from a logic model of it (§4.8), not yet from measurements on my clock; the measured values go in as the build reaches them.

4.1 Power

The RL1200 runs from a single +12 V DC input. The relays dominate its consumption, and how many are energised depends on the time shown, so the current varies minute to minute. From the logic model (§4.8), which counts every energised coil for every minute of a twelve-hour cycle:

Table 1 — The RL1200 runs from a single +12 V DC input. The relays dominate its consumption, and how many are energised depends on the time shown, so the current varies minute to minute. From the logic model (§4.8), which counts every energised coil for every minute of a twelve-hour cycle

Load	Average	Peak	Notes
Relays and LEDs	0.72 A	1.63 A	Peak at 12:59 during the 10-second clock pulse
Nixie supply, as designed (156 V, 33 kΩ)	~0.04 A		Four tubes at 0.48 mA
Nixie supply, Volume 2 values (174 V, 22 kΩ)	~0.12 A		Four tubes at 1.55 mA
CMOS timebase	negligible
Total (Volume 2 values)	~0.84 A (10 W)	~1.75 A

The model assumes a 275 Ω coil (43.6 mA when driven from 12 V, 19.8 mA when held through 330 Ω) and about 1 mA per LED. Treat it as an estimate until measured.

So: use a regulated 12 V supply rated for at least 2.5 A, with 3 A a comfortable choice. Two cautions:

• Regulation matters. The register timing (Volume 1, §1.3) and the hold current both scale with the supply voltage, and the 16 V electrolytics on the rail have only modest headroom over an unregulated adapter’s no-load voltage.
• No reverse-polarity protection. D34 on the board is the /CLK clamp, not a polarity diode. Use a connector that cannot be plugged in backwards.

About 10 W is dissipated continuously, most of it in relay coils spread across the board. The board runs warm, not hot; an enclosure needs some ventilation.

4.2 Setting the time

When power is applied, every storage relay starts released, so every register reads zero and the clock shows 01:00 (hour code 0 displays as 1; Volume 1, §1.6).

1. Move SW2 to SET. Each cycle of the set signal now runs the full register update, exactly as a real minute pulse does.
2. SW1 to FAST (8 Hz, eight minutes per second) to get close, then SLOW (1 Hz, one minute per second) for the last few minutes. Watch the binary LEDs and the tubes; the relays clatter continuously while setting.
3. Stop on the right minute and move SW2 back to RUN.

In FAST, each clock pulse is only 62.5 ms long. The relays need up to about 45 ms to settle after each edge (Volume 1, Figure 1.5), so FAST is near the edge of what the logic can follow. If FAST ever skips or miscounts, use SLOW.

The seconds cannot be zeroed. U2 and U3, the seconds counters, run freely from power-up and have no reset control: U2’s reset pin is tied to ground and U3’s is driven by its own count.¹ The displayed minute changes whenever the seconds LEDs pass 00, so the clock’s minute boundary sits at an arbitrary offset of up to a minute from true time. In practice, set the minute while watching a reference clock so the error is small, and accept a fixed offset of a few seconds. A seconds-reset button would need a trace cut at U2 and a diode into U3’s reset; it is a possible modification, not yet worked out or tested.

4.3 Accuracy

The relays add no timing error of their own: they count whatever pulse they are given. Accuracy is the crystal’s. The schematic does not specify Y1’s tolerance, and C3 (33 pF) is fixed, so there is no trimmer. As a guide:

1 ppm = 86.4 ms per day
10 ppm ≈ 0.86 s/day ≈ 26 s/month
30 ppm ≈ 2.6 s/day  ≈ 79 s/month

Measure it by comparing the seconds LEDs with a reference over a week. If the clock runs consistently fast or slow, C3’s value is the place to adjust the crystal’s load (a larger C3 slows the oscillator slightly), at the cost of experimentation; there are no pads for a trimmer.

4.4 Power cuts

There is no battery backup. Every bit of the time is held by a relay holding itself in, so the moment the 12 V fails, every storage relay drops and the time is lost. When power returns the clock shows 01:00 and runs from there, which is at least an unmistakable sign that it needs setting.

4.5 External clock input

J6 (EXT CLK) connects directly to the /CLK line that drives the six sampling relays.¹ Despite the datasheet’s “active low external 1Hz reference”,² each low pulse there advances the clock one minute: it is a once-a-minute input. Anything driving it must:

• Sink about 0.26 A: six sampling coils at 43.6 mA each, an inductive load.
• Hold the pulse low for tens of milliseconds at least, long enough for the sampling and storage relays to operate (Volume 1, §1.3). The on-board timebase uses ten seconds; 100 ms or more is a sensible minimum for an external source.
• Be an open-drain or open-collector output, because Q1 shares the line. Q1 pulls /CLK low in both positions of SW2 (in RUN for the first ten seconds of each minute, in SET at 1 or 8 Hz), so an external source can only have sole control if Q1 is left unfitted. Its gate has no pull-down on the schematic, so do not simply lift R33 and leave the gate floating.

A GPS- or mains-derived minute pulse is a plausible accuracy upgrade through this input. It is not designed or tested here.

4.6 Troubleshooting by symptom

The board helps: every register bit has an LED, and the three CLR signals each light an LED (D10 for CLR 1 MIN, D3 for CLR 10 MIN, D1 for CLR 12 HR). Most faults can be found by comparing what the LEDs show with what Volume 1 says they should.

Table 2 — 4.6 Troubleshooting by symptom

Symptom	Likely cause	Check
Seconds LEDs do not count	Oscillator not starting, U1 or U2	Y1, C3, C9, R4, R7; 1 Hz at U1 pin 14
Seconds count but nothing happens at :00	/CLK not pulling low	SW2 in RUN; Q1, R33; /CLK low for 10 s (Volume 3, Stage 2)
One register bit never sets, or never clears	Its sampling path	The 470 µF capacitor (polarity, value, age), its 10 Ω resistor, the sampling relay contact
A bit sets, then falls back	Its hold path	The 330 Ω holding resistor; the storage relay’s output contact
A digit counts wrongly (skips or repeats values)	One +1 relay	Read Q on the LEDs, work out the expected next value, then check that bit’s XOR relay and its carry contact
Minutes do not roll 9 → 0, or the 10-minute digit never advances	CLR_1MIN	D10 should light at minute x9; K37 pole 1, K23/K24
Wrong at the hour, or wrong at 12:59 → 1:00	CLR_10MIN or CLR_HR	D3 and D1; K36/K44; K48/K41/K35
One digit never appears, or the wrong digit lights	Decoder relay or tube wiring	Volume 3, §3.5 (J4’s order differs from the others)
Hours all off by one	J4 wired in J5’s order	Volume 3, §3.5
A digit sometimes stays dark after the minute changes	HV too low to strike the new cathode	Volume 2, findings 1 and 2
All tubes dim, glow not covering the numerals	Tube current too low	Volume 2 anode resistor and HV values
Clock runs sixty times fast	A 1 Hz signal on J6, or SW2 left in SET	§4.5

4.7 Upkeep and the case

Relays are a wear item. The six sampling relays operate once a minute, which is 525,600 operations a year. The 1-minute register’s bit 0 storage relay pulls in every other minute, about 263,000 times a year. Most other relays work far less. Compare those figures with Omron’s mechanical endurance rating for the G2R-2 when choosing whether to socket the relays (Volume 3, §3.3).

Electrolytics age with heat. The ten 470 µF sampling capacitors set the register timing margins. If a bit starts to misbehave after years of running, suspect them first.

The case. The designer mounted his board and tubes on an 8 × 12 inch wooden cutting board and hung it on the wall.³ An open board is the point of a relay clock, but the NIXIE SUPPLY strip, the anode resistors and the tube wiring are live at over 150 V. Put a clear cover over at least those, and keep it out of reach of children and pets.

4.8 The logic model

The current figures in §4.1, and the claim in Volume 1 that the clock counts correctly through every minute of twelve hours, come from a small Python model of the schematic, kept with this clock as 05-resources/model/rl1200_logic_model.py. It encodes each relay exactly as traced from the schematic: storage relays energised when their bit is 1; +1 relays energised when their two coil terminals differ; clear relays when their CLR signal is true; decoder relays when their bit is 1; sampling relays during the clock pulse. The decoder trees are encoded branch by branch, so the model checks the decoders as well as the counting.

Run over all 720 minutes from 01:00, it produces the displayed times 01:00, 01:01 … 12:59 and returns to 01:00, matching a real clock in every minute, with every decoder selecting the correct cathode. It also gives the energised-coil count per minute, from which:

held coil:    12 V / (275 Ω + 330 Ω) = 19.8 mA  (coil at 5.45 V)
driven coil:  12 V / 275 Ω            = 43.6 mA
worst case:   7 held + 34 driven coils + LEDs = 1.63 A  at 12:59, during the pulse
12-hour mean: 0.72 A (pulse for 10 s of every 60)

Where the model and the real clock disagree, the real clock wins, and the model gets fixed.

4.9 References (Vol 4)

Footnotes

1. Catahoula Technologies, 12-hour 4-digit relay clock schematic, 2021-08-10, held in this clock’s 02-inputs/Designer - Catahoula RL1200/. ↩ ↩²

2. Catahoula Technologies, RL1200 – 4-digit 12-hour nixie clock datasheet, 2021-08-09, page 2, “EXT IN” input ports. ↩

3. Jon Stanley, “Relay Logic Projects”, electronixandmore.com, https://www.electronixandmore.com/projects/relaylogic/index.html: “I mounted the board and nixies on a 8x12” wooden cutting board and hung it up on the wall.” ↩