Build A — Dutchtronix AVR Scope Clock (owned)

Decades after the last electrostatic oscilloscope rolled off a production line, a single small green PCB stamped “Dutchtronix Clock 3.1 2008” did more than any other artifact to turn the surplus scope tube on a hobbyist’s shelf into a clock. The Dutchtronix AVR Oscilloscope Clock is the design that the modern hobby category is built around: an ATmega microcontroller, a single dual-output DAC, a real-time-clock chip with a coin-cell backup, and a pair of BNC outputs that you plug straight into the X and Y inputs of any oscilloscope you already own. There is no high-voltage supply on this board at all — the scope you connect it to supplies the CRT, the high voltage, and the deflection amplifiers, and the Dutchtronix board supplies only the X, Y, and intensity waveforms. That single architectural decision is what made it cheap, safe to build, and universally compatible, and it is why this is the unit the owner of this hub reaches for first when explaining what a scope clock is. This volume documents the owned unit: what the board is, what the six designer PDFs in the source folder actually say, which firmware images and source archive are on hand, how to flash them, and what it is like to live with the clock next to the OSC4.4 (the other owned build, covered in Vol 8).

7.1 What the Dutchtronix AVR Scope Clock is

The Dutchtronix is best understood as the opposite design philosophy from the OSC4.4 in Vol 8 and the from-scratch builds in Vol 10. Where those are complete clocks — they carry their own CRT, their own high-voltage supply, and their own deflection amplifiers — the Dutchtronix is a vector signal source. It generates the three signals a vector display needs (a horizontal-deflection voltage, a vertical-deflection voltage, and a beam-intensity control) and hands them off, through ordinary BNC connectors, to a bench oscilloscope set to X-Y mode. The scope is the display; the Dutchtronix board is the brain.

This is the design Jan-Bart “Dutchtronix” first published in 2008 (the schematic title block reads “Oclock2008”, dated 7/7/2008), and the owned unit is the Hardware 3.1 revision, whose silkscreen reads “Dutchtronix Clock 3.1 2008”. As Vol 1 and Vol 2 recount, this was the design that launched the category; the broader history and the wider field of descendants are told in Vol 2, and the buy-it-finished and clone-board alternatives in Vol 9.

7.1.1 The board, subsystem by subsystem

Reading the Hardware 3.1 schematic and the parts list together, the board breaks into five functional blocks, all running from a single low-voltage rail:

• The microcontroller (IC1). An ATmega328P-20PU clocked by a 20 MHz crystal (Q1) with two 22 pF loading capacitors (C3, C4). The “-20PU” suffix and the 20 MHz crystal matter: the firmware’s DDS and vector-drawing loops are written for a 20 MHz part, not the 16 MHz of a stock Arduino, and the Makefile in the source archive confirms -DF_CPU=20000000UL. The chip is socketed in a 28-pin DIP socket and ships pre-programmed with both the bootloader and the clock firmware.
• The DAC (IC2). A single Analog Devices AD7302 — a dual 8-bit, voltage-output DAC in a 20-pin package. One channel drives the X output, the other the Y output. The two outputs leave the board on the turret terminals and BNC connectors marked CH1 and CH2. The AD7302 takes a reference set by trimpot R8; the assembly notes flag that R8 (and series resistor R7) are silkscreened “2K” but are actually 1K, and that the kit ships 1K parts — a documented errata on this revision.
• The real-time clock (IC3). An NXP/Philips PCF8563 RTC on the AVR’s I²C (TWI) bus, with its own 32.768 kHz watch crystal (Q4) and a lithium coin-cell backup (BATTERY) gated by Schottky diodes D3/D4 (BAT-42 or BAT-85). The PCF8563 keeps time across power-downs; the source archive’s ClkConfig.h shows the firmware can alternatively be built for a DS1307 RTC (the Sparkfun “O-Clock” variant), which is why the config file carries both #define pcf8563 and #define ds1307 switches.
• The serial interface (IC5 and the optional IC6). A HIN232ACP (a MAX232-class RS-232 level converter) provides a true ±RS-232 port on the on-board female DB-9 (X1) and on a 3-pin polarized header marked RS232. An optional, unpopulated FT232RL (IC6) plus its support parts (C9, C10, C11, L1, and the USB connector X2) can be fitted to add a native USB virtual-COM-port; the Clock kit ships these positions empty.
• The power and housekeeping block. A barrel jack (J1, 7–15 V DC, centre-positive, 5.5 mm OD) feeds an LM7805 (IC4) through a 1N4001 reverse-polarity diode (D5); a VCCSELECT header lets you instead feed regulated 5 V directly on the VCCPOWER 2-pin header. A power switch (S3), a red power LED (D1), a green status/user LED (D2), and two momentary tactile switches (S1, S2) for the user interface round it out. A 2N3904 (Q3) inverts the intensity (“Z”) signal for scopes whose Z-axis input expects the opposite polarity.

FIGURE SLOT 7.1 — The owned Dutchtronix Hardware 3.1 board, top-down, with the major ICs labelled (ATmega328P, AD7302 DAC, PCF8563 RTC, HIN232 RS-232, optional FT232RL footprint) and the CH1/CH2/GND turret terminals and DB-9 called out. Suggested: an owner build photo (board is on hand), or the assembled-board photo from the Assembly PDF.

7.1.2 What is not on the board

It is worth stating plainly, because it is the whole point: there is no high-voltage supply, no CRT, no deflection amplifier, and no video/Z amplifier on the Dutchtronix board. Everything Vols 3, 4, and 6 describe — the anode/focus/bias rails, the differential X/Y deflection amps, the cathode/grid video amp, the tube itself — lives inside the oscilloscope you connect to. This is why the Dutchtronix is the safest entry point in the whole series (it never produces more than 15 V), and also why it is the least self-contained: without a scope, it draws nothing. The trade-off versus a self-contained build like the OSC4.4 is discussed in § 7.6.

7.2 The document set on hand

The owned unit comes with the full designer document set — six PDFs, each a page from the original Dutchtronix web manual. They are the primary source for this volume, and the exact pin-level and procedural detail lives in them; this section summarises each accurately and points back to the PDF for the fine print.

7.2.1 Assembly (AVR Scope Clock Assembly.pdf)

The assembly guide is a build-by-photo document for the Hardware 3.1 kit rather than a step-numbered manual. Its substance is in the cautions and the parts list:

• Resistor identification. It gives the colour codes: R1–R5 are 10K (brown-black-orange), R6/R7/R14 are 1K (brown-black-red), R9 is 470R (yellow-violet-brown), R13 is 4K7 (yellow-violet-red), with the 1% four-band equivalents listed too.
• The R7/R8 errata (noted again in § 7.1.1): silkscreened “2K”, actually 1K, and 1K is what the kit supplies.
• Build order. Turret terminals CH1/CH2 first (soldered from the bottom), then IC sockets (tack two opposite pins, check seating, then finish), then ascending component height; large connectors (the two BNCs and the DB-9) last.
• Orientation rules. All ICs face pin-1 to the left of the PCB. The polarized POWER and RS232 headers install with the flat back toward the board centre. Electrolytics C6, C7, C8, C17 are polarized; the rest (C1, C2, C5, C12–C16, C18, plus the 22 pF C3/C4) are ceramic. The battery’s lettered face is the + side.
• Shunt/jumper setup. Install a shunt on the 1PPS header; on VCCSELECT, shunt the two pins nearest the VCCPOWER header (this selects the on-board 7805 path); on TXROUTE and RXROUTE, shunt the right-most pins (next to the RS232 header) for the on-board RS-232 path.
• A genuinely good bring-up procedure. Do not install the four ICs first. With sockets empty, verify ~3 V at the D3/D4 junction (the backup battery), then apply power and check the per-IC supply pins — IC1 pin 7, IC2 pin 15, IC3 pin 8, IC4 pin 16 — before seating any chips. Only when those rails are good do you insert the ICs (all pin-1 left). This is exactly the kind of staged power-up the safety discipline in Vol 12 preaches, here applied to a low-voltage board.
• A first-power-up note that the RTC may report low-battery for a few cycles, cleared by setting the time and resetting.

FIGURE SLOT 7.2 — The Hardware 3.1 parts-layout / assembled board, annotated with the bring-up test points (IC1·7, IC2·15, IC3·8, IC4·16 and the D3/D4 battery junction). Suggested: the parts-list page or assembled-board photo from the Assembly PDF, or an owner build photo.

7.2.2 Schematics (AVR Scope Clock Schematics.pdf)

The schematics PDF is two sheets: the full single-page schematic (“Oclock2008”, Sheet 1/1, dated 7/7/2008) and the PCB artwork. Because Vols 3–5 are the engineering reference, the useful thing to extract here is how the Dutchtronix maps onto those generic blocks:

• MCU/DAC path. The ATmega328P’s PORTB and PORTC lines (labelled PORTB[0..3] and PORTC[0..3] on the sheet) carry the parallel data and the DACLDAC / DACSELECT / DACWR control lines into the AD7302; the AD7302’s X-OUT and Y-OUT go to UREF-referenced output stages and out to CH1/CH2. This is the “MCU + parallel DAC” topology Vol 5 describes — the AD7302 is written as a memory-mapped peripheral, which is why the render loop is timed in CPU cycles.
• No deflection/HV section appears on the sheet, because there isn’t one — see § 7.1.2. The “deflection” and “video” sub-circuits a reader might look for (Vol 4) are absent by design; the only analog output conditioning is the DAC reference network (R7/R8, UREF) and the Q3/R13 intensity inverter feeding the ZINV pin.
• Housekeeping. The PCF8563 (with Q4 32 kHz crystal and the battery/diode network), the HIN232/MAX232A with its charge-pump capacitors (C12–C16), the FT232RL USB block (drawn but unpopulated on the Clock kit), the 7805 regulator with D5, and the 1PPS/RXROUTE/TXROUTE jumper headers are all on the one sheet.

For exact pin numbers, net names, and the DAC control timing, read the schematic PDF directly — it is legible at the component level and is the authoritative wiring reference. The 2008 schematic is also re-exported in the 2023 H31 archive discussed in § 7.4.

7.2.3 Operating (AVR Scope Clock Operating.pdf)

The operating manual is the H3-1 “enhanced operating instructions” and is the most useful day-to-day document. Its key content:

• Powering and connecting. Wall-wart 7–15 V centre-positive into J1, or regulated 5 V on the VCCPOWER header (the negative pin is the one marked “1” on the connector body; the header is keyed so reverse connection is impossible if the cable is built correctly).
• Scope setup. Put the scope in X-Y mode, both channels DC-coupled at 0.5 V/division. Turn R8 fully counter-clockwise (maximum image), then clockwise to fit the screen; fine-square the image with the scope’s VAR control to about 8 divisions. Note the convention warning: most scopes treat CH1 as X and CH2 as Y, but some (the Tektronix 485 is the cited example) reverse it, so you may have to swap probes. In 10× probe mode, adjust probe compensation if the image looks distorted.
• The two-button UI. Everything is driven from S1 and S2 with long (>1 s) and short (<1 s) pushes. S1 short enters the on-screen Menu; S1 long enters Time/Date Set. S2 short shows the help screen; S2 long reboots the clock (the quick way out of any menu). In Set mode, S1 short increments the current field (hold for auto-repeat) and S2 short advances to the next field; date entry is Year→Month→Day so the firmware can validate day counts and leap years. Change mode times out after 30 s, and during a time change an S2 short cancels and restores the RTC time — a deliberate “I changed my mind” escape.
• The face/menu options (firmware V4.0 table). The manual reproduces the full menu. The display-shaping options are Num (the numeric readout: 12 hr / 24 hr / Hex / Date / Alarm / Off) and Dial (the clock face: 12 hr / 24 hr / Rom[an] / Dig[ital] / Bin[ary] / Min). The rest configure behaviour: GPS (NMEA input with a −12..+12 timezone offset), DST (USA / EU / Off auto daylight saving), App (which application runs: Clock / Cal / Term / Gen / Demo / Boot), PPS (1 Hz or 4096 Hz pulse-per-second output with a −4..+4 software accuracy trim), Chrono (fractional-seconds display), Alarm, Led (On / Morse / Debug / Off), BurnIn (0..9, the screen-shift burn-in-prevention rate), Play (Reverse / Fast-Forward / Fast-Reverse “fun” modes), Reset (re-initialise the ATmega328P EEPROM to a virgin state), Baud (serial rate), and Name (a user-name / day-of-week display).

FIGURE SLOT 7.4 — A montage of the selectable faces (analog 12 hr dial, Roman dial, digital seven-segment, binary clock) photographed off a scope screen. Suggested: owner photos of the powered clock cycling Dial modes.

7.2.4 Firmware Update (AVR Scope Clock Firmware Update.pdf)

The update guide applies to Hardware 3-1, firmware 3.5 and up, ATmega328P. The mechanism is the important part and is summarised in § 7.5; in brief, the chip ships with a 1 KB stk500v1 bootloader (a size-reduced pre-UNO Arduino bootloader leaving 31 KB for the application), and you reflash it over the serial port with avrdude (from the WinAVR suite) using a supplied batch file. The PDF also documents the serial-cable options and the S1-held-at-power-on entry into boot mode.

7.2.5 Function generator (AVR Scope Clock FuncGen.pdf)

Since firmware V3.5 the board doubles as a DDS function generator, a port of Jesper Hansen’s AVR mini-DDS design. It synthesises sine, sawtooth, triangle, and square waveforms on the CH1 output. Because the Dutchtronix uses a real DAC (the AD7302) rather than Hansen’s resistor-ladder DAC, the dots are precise but the waveforms look “blocky”, and a DAC step costs more CPU cycles. The PDF gives concrete numbers: firmware V4.0 trimmed the DDS step to 12 CPU cycles, giving a synthesizer constant of 1,666,666 (20,000,000 ÷ 12), versus 1,538,461 (20,000,000 ÷ 13) for V3.6 — values you type into the ddscontrol Windows program’s preferences (DDS resolution 24-bit). Because the DDS loop is too tight to poll the buttons, the generator is controlled only over the serial link from the PC: enter Menu → App → Gen → activate, then use ddscontrol or its ±1 / ±100 / ±10,000 Hz arrow buttons. The PDF notes that deleting a stale minidds.ini fixes occasional ddscontrol misbehaviour.

7.2.6 Terminal (AVR Scope Clock Terminal.pdf)

The most surprising application: the board turns the scope into a 20-character × 13/14-line serial text terminal (the “Dutchtronix Terminal”), again built into firmware V3.5+. It shows the full 7-bit ASCII set, interprets BS/HT/LF/CR with a clever delayed-linefeed scheme (so a status line ending in a bare CR overwrites in place — handy for a refreshing GPS fix), has a blinking cursor that appears ~1 s after the last character, scrolls fast enough to keep up with ~38,400 bps, and shows the clock’s numeric readout on the bottom line (which can be turned off to recover the 14th line). Crucially the PDF explains the two gotchas that trip everyone up:

• Levels. The DB-9 / RS232 header are true RS-232 levels (−12 V = 1, +12 V = 0); raw TTL-level serial is available on the centre pin of the RXROUTE header. Pick the level that matches the device feeding the terminal.
• Crossover. The sender’s TX must reach the clock’s RX (DB-9 pin 3 / header pin 3); a straight PC cable usually won’t work, so make a custom cable or add a null-modem adapter.

Firmware V4.0 added persistent vector graphics to the terminal: up to 128 line vectors (0–255 pixel coordinates, X=0 left, Y=0 top) on a separate plane from the text, driven by a small escape-code protocol (0xFF followed by a sub-command: VectorEntry 0xF0, VectorRange 0xF1, SetCursorPosition 0xF2, SetCursorControl 0xF3, SetClockLine 0xF4, SetBurnIn 0xF5, SetTermCtrl 0xF6). The included Asteroids demo (Christopher Ladden’s vector game, runnable from a PC at 115,200 bps or an ATmega2560 STK-600 at 250,000 bps) drives this protocol and is shipped in source form with the firmware. The PDF closes with an honest note on display quality: heavy serial traffic produces a bright “parking” dot at the lower-right because the AVR can’t move the beam while servicing a burst of interrupts, and the board’s intensity (“Z”) control is the cure.

7.3 Firmware images and source on hand

Three firmware artifacts ship with the owned unit, spanning the design’s whole supported life:

• ScopeClock4-V2-12-18-2015.hex — a December 2015 build of the V2-era clock firmware, an Intel-HEX application image (1899 records, 16-bit addressing, comfortably inside the 328P’s 32 KB flash). This is an application-only image to be loaded through the bootloader.
• ScopeClock4.V3.clock+boot.03-31-2021.hex — a March 2021 build labelled “clock+boot”, i.e. the application and the bootloader combined into one image (988 records, single 64 K segment). The “+boot” naming matters: this image is meant to be burned with a hardware programmer through the ISP header, because it (re)writes the bootloader region near the top of flash that the serial path normally protects. The serial/avrdude path described in § 7.5 normally flashes application-only images and leaves the existing bootloader in place.
• ScopeClockSourceV4.3.zip — the complete V4.3 source release (dated 31 March 2021). It is a real AVR-GCC project: 29 files including the C modules (ClkApp.c, ClkMenu.c, ClkGen.c, ClkTerm.c, ClkGPS.c, ClkDSTime.c, ClkDemo.c, the I²C master twimaster.c, etc.), the hand-written assembly render core clkrender.s / ClkRender.o (the cycle-counted vector-drawing loop), the vector and font tables (vecttable.inc, vectsamples.inc, font8x5.inc), the build switches in ClkConfig.h, and a default/Makefile. The readme states it builds with AVR Studio 4.18 (build 700) and WinAVR-20100110, targets the atmega328p at F_CPU=20000000UL, and that switching to the Sparkfun O-Clock V1.1 is a one-line change in ClkConfig.h (flip ds1307/pcf8563). This is the version the Firmware Update PDF refers to as “current V4.3”, and it is newer than either bundled hex — so the most up-to-date binary on hand must be built from this source, not flashed from the 2015/2021 hex files.

The version progression visible across the documents — V3.4-and-earlier button scheme → V3.5 (adds the terminal, function generator, and the new long/short button UI) → V3.6 (DDS at 13 cycles) → V4.0 (12-cycle DDS, persistent vectors, the full menu table) → V4.3 (the source release) — is the practical changelog. To see exactly which version a unit runs, do a short S1 or S2 push; the version number prints above the menu/help screen.

The vector-drawing engine these images contain is the same engine Vol 5 dissects in the abstract; the Dutchtronix clkrender.s is one of the cleanest real-world examples of a cycle-counted AVR vector loop, and is worth reading alongside that volume.

7.4 The 2023 H31 board and gerber files

Two further archives in the folder are manufacturing files, not firmware:

• Oclock2023-H31.zip contains Oclock2008.sch and Oclock2008.brd — the EAGLE schematic and board-layout source files for the design, re-saved on 2 May 2023. (The base name “Oclock2008” and “H31” tie them to the same Hardware 3.1 design as the owned board.)
• Oclock2023-H31-Gerber.zip contains a full Gerber + Excellon fabrication set: .cmp (component/top copper), .sol (solder/bottom copper), .plc (top silkscreen), .stc/.sts (top/bottom soldermask), the .drd drill data and .dri/.gpi photoplotter info files — the standard CAM output of EAGLE’s gerb274x + excellon jobs.

Their purpose is reproduction: with these files a builder can have a fresh Hardware-3.1-class board fabricated at any PCB house (the 2023 date suggests a re-export so the design could be re-fabbed long after the original kits sold out). They are not needed to build or operate the owned unit, but they make the design self-perpetuating — and they are the bridge to the “roll your own board” path in Vol 10, since a builder could take this proven layout as a starting point. Anyone fabricating from them should confirm the EAGLE version compatibility and re-run a design-rule check against their fab’s capabilities before ordering.

7.5 Flashing the firmware (procedure and notes)

The update path documented in the Firmware Update PDF is the normal way to change firmware on the owned unit, and it is pleasantly low-risk because nothing here is at high voltage:

1. Tools. Get the designer’s uploadm328p zip (it bundles avrdude from WinAVR and the current V4.3 hex). avrdude talks to the on-board 1 KB stk500v1 bootloader.
2. Cable. Easiest is a standard DB-9 serial cable (a DTE-to-DCE crossover). Alternatively build a custom 3-pin cable to the RS232 header — the PDF gives the wiring as 3-pin header: 1=GND, 2=out/RXpc, 3=in/TXpc; DB-9: 5=GND, 2=RX, 3=TX, with header pin 1 being the right-most pin. If the optional FT232RL/USB parts are fitted, a normal USB A-B cable works (install FTDI drivers; set the RX/TX route shunts to USB). USB-serial dongles “work, but results are mixed”.
3. Edit the batch file. In uploadm328p.bat, set COMPORT to your port and HEXFILE to the application hex. Make sure nothing else (a terminal program, or worse a GPS) is holding the port.
4. Enter boot mode. Power-cycle with S3, and hold S1 down while switching on. The board enters boot-load mode — LED D2 flashes fast and the screen is blank. (Push S2 to back out without flashing.)
5. Run uploadm328p.bat. The PDF warns that an avrdude limitation may require turning off the verify (-V) option in the script.

Two notes the PDF makes that are easy to miss. First, the serial/bootloader path flashes the application and leaves the bootloader intact — this is the normal route and is what the 2015 V2 application hex is for. Second, builders with an AVR ISP programmer can program the ATmega328P directly through the (optional, not-included) 10-pin ISP header, which is the route for the clock+boot image and the only way to restore a board whose bootloader has been erased. The PDFs in hand do not print the exact fuse-byte values for the 328P (they defer to the designer’s online FAQ), so if you ISP-program a blank chip, get the fuse settings from the Dutchtronix FAQ rather than guessing — the 20 MHz external-crystal clock source and the bootloader-size/boot-reset-vector fuses must match the firmware’s assumptions. Vol 12’s calibration section covers the post-flash step of re-trimming R8 and re-fitting the image to the scope.

7.6 Living with it, and how it compares to the OSC4.4

In daily use the Dutchtronix is the most flexible of the owned clocks and the least finished. Because the display is whatever oscilloscope it is plugged into, the same board can look completely different on a 3-inch Tektronix portable, a big lab scope, or a salvaged DG7-class round tube driven through a homemade X-Y amplifier — and it can switch between an analog dial, a Roman face, seven-segment digits, and a binary clock at the push of a button, then become a function generator or an ASCII terminal, or play Asteroids. That versatility is the reason it is the right teaching unit and the right thing to demonstrate the principles in Vols 4 and 5 against: you can probe CH1/CH2 with a second scope and see the X and Y waveforms the firmware emits.

The quirks are the flip side of the same coin. There is the bright parking-dot under heavy serial load (§ 7.2.6), the “blocky” DDS waveforms from clocking an 8-bit DAC through a tight loop (§ 7.2.5), and the standing requirement to own a scope and leave it in X-Y mode to have a clock at all — a Dutchtronix on its own is just a green PCB. Image quality is also hostage to the scope: a tired CRT or a scope with mediocre X-Y bandwidth flatters none of the firmware’s precision, and the R8 trim plus the scope’s own gain controls have to be re-set whenever you move it to a different instrument.

Against the OSC4.4 (Vol 8), the contrast is clean. The OSC4.4 is a complete clock: it carries its own DG7-32 or 6Lo1i CRT, its own ~300 V supply, its own transistor wave-shaper and deflection drive, and optional Wi-Fi and GPS time-sync modules, so it is a finished object you put on a shelf and forget — but every one of those subsystems is a real high-voltage hazard to build and service (the discharge-and-one-hand discipline of Vol 12 is mandatory for it, and merely good practice for the Dutchtronix). Where the OSC4.4 is self-contained, shelf-ready, and dangerous, the Dutchtronix is dependent, bench-bound, and safe. The OSC4.4 wins for a permanent display and for network/GPS time without a PC; the Dutchtronix wins for learning, for hacking (terminal, function generator, vector games), for risk-free assembly, and for compatibility with whatever tube-and-scope a builder already has. The honest recommendation that falls out of owning both: build the Dutchtronix first to understand the vector-drawing problem at low voltage, then build the OSC4.4 when you want a clock that stands on its own — which is exactly the ordering Vol 1’s decision tree suggests.

7.7 What the in-folder docs do and don’t specify

To set reader expectations honestly: the six PDFs are excellent on assembly, operation, flashing, and the serial applications, and the schematic is legible to the component level. What they deliberately defer to the (online) Dutchtronix FAQ and the source archive are: the exact ATmega328P fuse bytes, the per-pin DAC control timing (read it from clkrender.s and the AD7302 datasheet), the precise scope drive levels in volts (the firmware emits a 0–full-scale DAC swing into the scope’s high-impedance X-Y input; the actual volts-per-division mapping is set by R8 and the scope, per § 7.2.3, not stated as a fixed number), and any CRT/high-voltage data (there is none on this board by design). For all of those, go to the original PDFs in 02-inputs/A - Dutchtronix AVR Scope Clock (I have this)/, the V4.3 source, and the designer’s FAQ. This volume reproduces the values the documents do state and flags, rather than invents, the ones they don’t.

7.8 References (Vol 7)

• Dutchtronix AVR Oscilloscope Clock — AVR Scope Clock Assembly.pdf (Hardware 3.1 kit assembly instructions and parts list). In 02-inputs/A - Dutchtronix AVR Scope Clock (I have this)/.
• Dutchtronix — AVR Scope Clock Schematics.pdf (Oclock2008 schematic sheet 1/1 dated 7/7/2008, and the Hardware 3.1 PCB artwork). Same folder.
• Dutchtronix — AVR Scope Clock Operating.pdf (H3-1 enhanced operating instructions; button UI, time/date set, the V4.0 menu/face table). Same folder.
• Dutchtronix — AVR Scope Clock Firmware Update.pdf (stk500v1 bootloader, avrdude/WinAVR procedure, serial-cable wiring, boot-mode entry). Same folder.
• Dutchtronix — AVR Scope Clock FuncGen.pdf (DDS function-generator app, Jesper Hansen port, ddscontrol settings, synthesizer constants). Same folder.
• Dutchtronix — AVR Scope Clock Terminal.pdf (serial terminal app, RS-232/TTL levels, delayed-LF handling, V4.0 vector-graphics escape protocol, Asteroids demo). Same folder.
• Dutchtronix — firmware images ScopeClock4-V2-12-18-2015.hex, ScopeClock4.V3.clock+boot.03-31-2021.hex, and source archive ScopeClockSourceV4.3.zip (readme, AVR-GCC project, ClkConfig.h, clkrender.s). Same folder.
• Dutchtronix — 2023 design re-export: Oclock2023-H31.zip (EAGLE .sch/.brd) and Oclock2023-H31-Gerber.zip (gerber + Excellon fab set). Same folder.
• Analog Devices, AD7302 dual 8-bit voltage-output DAC datasheet — for the DAC control/timing detail not reproduced in the PDFs. analog.com.
• NXP, PCF8563 real-time clock/calendar datasheet — for the RTC and I²C interface detail. nxp.com.
• Dutchtronix AVR Oscilloscope Clock FAQ (the designer’s online manual referenced throughout the PDFs) — authoritative source for fuse bytes and procedures not in the in-folder documents.